| 摘要 |
A class AB transconductor circuit comprises complementary PMOS and NMOS transistors ( 10, 12 ) having their source-drain paths connected in series between first and second voltage supply rails ( 14, 16 ). An output terminal ( 20 ) is coupled to a junction of said series connected source-drain paths. Gate electrodes of the PMOS and NMOS transistors are coupled to an input terminal ( 18 ) by way of respective first and second paths each of which includes first and second bias voltage supply sources ( 32, 34 ). The quiescent gate voltages of the PMOS and NMOS are offset from the quiescent input voltage by the equal and opposite voltages (V<SUB>b</SUB>) of the first and second bias voltage supply sources thereby reducing the apparent threshold voltage (V<SUB>t</SUB>') of the PMOS and NMOS transistors by the value of the bias voltage supply sources. Balanced class AB transconductor circuits are also disclosed.
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