发明名称 |
Semiconductor devices having post passivation interconnections with a second connection pattern |
摘要 |
An integrated circuit having post passivation interconnections with a second connection pattern is disclosed. A passivation layer (preferably made of a non-oxide material) is formed over the integrated circuit already having a first plurality of contact pads in a first connection pattern. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer with a thickness substantially smaller than a thickness of the passivation layer. A post passivation metal layer is deposited over the buffer layer. A second plurality of contact pads as part of the second connection pattern is formed in the post passivation metal layer. |
申请公布号 |
US2006145332(A1) |
申请公布日期 |
2006.07.06 |
申请号 |
US20060363813 |
申请日期 |
2006.02.28 |
申请人 |
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发明人 |
CHENG HSI-KUEI;CHIEN HUNG-JU;CHAN HSUN-CHANG;CHEN CHU-CHANG;WANG YING-LANG;SU CHIN-HAO;FENG HSIEN-PING;CHANG SHIH-TZUNG |
分类号 |
H01L23/12;H01L21/4763;H01L21/60;H01L23/31;H01L23/485 |
主分类号 |
H01L23/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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