| 摘要 |
<p>A Sweeney Robertson Tocher (SRT) divider and a square root extractor of floating point double-precision bit width, including a selector of single-precision and double-precision, a carry propagation adder (CPA) for conducting carry propagation of a partial remainder, a quotient digit selector circuit for making selection on a quotient digit, and a selector of a divisor or a partial square root extractor circuit, in a lower side thereof. A selector for selecting the propagation of carry between a carry save adder (CSA) in the upper side and the lower side thereof is provided, and a selector of a starting position within a quotient production circuit is provided, thereby enabling the execution of two (2) calculations, such as, division or square root extraction of the floating point single-precision, at the same time, but without increasing the bit width of a computing unit. Also, with the square root extraction, it is possible to execute two (2) calculations of single-precision in parallel, in a similar manner, by adding a partial square root extraction circuit thereinto.</p> |
