Microtlb and micro tag for reducing power in a processor

摘要

A processor (10) comprises a cache (16), a first TLB (30), and a tag circuit (36). The cache (16) comprises a data memory (20) storing a plurality of cache lines and a tag memory (22) storing a plurality of tags. The first TLB (30) stores a plurality of page portions of virtual addresses identifying a plurality of virtual pages for which physical address translations are stored in the first TLB (30). The tag circuit (36) is configured to identify one or more of the plurality of cache lines that are stored in the cache (16) and are within the plurality of virtual pages. In response to a hit by a first virtual address in the first TLB (30) and a hit by the first virtual address in the tag circuit (36), the tag circuit (36) is configured to prevent a read of the tag memory (22) in the cache (16).