发明名称 Method and system for optimized FIFO full conduction control
摘要 Method and system for generating an optimized full signal in a FIFO device. In one embodiment of the present invention, the optimized full signal control circuit checks the storage capacity of the FIFO memory by aggregating the number of occupied word entries and the number of occupied pipelines.
申请公布号 US7072998(B2) 申请公布日期 2006.07.04
申请号 US20030436822 申请日期 2003.05.13
申请人 VIA TECHNOLOGIES, INC. 发明人 HUANG HSILIN
分类号 G06F3/00;G06F12/00;G06F13/42 主分类号 G06F3/00
代理机构 代理人
主权项
地址