| 摘要 |
A technique to form a structure with a rough topography in a planarized semiconductor process. The rough topography is formed by creating cored contacts. Subsequent process layers may be further stacked on top of the cored contacts in order to augment the nonplanar characteristics of the cored contacts. This rough topography structure may be used to align integrated circuits and wafers. An integrated circuit may be laser aligned using this alignment structure.
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