发明名称 |
Clock timing recovery using arbitrary sampling frequency |
摘要 |
A bit timing signal is regenerated from an encoded digital signal in a receiver using a predetermined sample rate F<SUB>s</SUB>. An input pulse signal is generated in response to predetermined transitions of the encoded digital signal. A clock count signal is generated having a variable clock period according to cyclical counting of the clock count signal up to a count value S at the predetermined sample rate, the count value alternating between an upper value S<SUB>u </SUB>and a lower value S<SUB>l </SUB>so that the variable clock period has an average length substantially equal to a data bit period of the encoded digital signal. The clock count signal is synchronized with the encoded digital signal by 1) counting the input pulse signals to generate a pulse count, 2) counting sampling periods between successive input pulse signals to generate a sample count, and 3) generating a sync signal if the pulse count is greater than a pulse threshold and the sample count is greater than a sample threshold. The clock count signal and the pulse count are reset in response to the sync signal.
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申请公布号 |
US7072431(B2) |
申请公布日期 |
2006.07.04 |
申请号 |
US20020284231 |
申请日期 |
2002.10.30 |
申请人 |
VISTEON GLOBAL TECHNOLOGIES, INC. |
发明人 |
WANG VINCENT;WHIKEHART J. WILLIAM;WHITECAR JOHN ELLIOTT |
分类号 |
H04L7/00;H04H40/27;H04L7/033;H04L25/06 |
主分类号 |
H04L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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