| 摘要 |
Methods of fabricating an MIM capacitor and a dual damascene structure of a semiconductor device are disclosed. According to one example, a method includes depositing a first insulating layer on a semiconductor substrate; forming a lower interconnect through the first insulating layer; sequentially depositing a second insulating layer, a third insulating layer, and a fourth insulating layer; forming a first mask pattern over the fourth insulating layer; forming a first dual damascene pattern by etching the fourth insulating layer; depositing a fifth insulating layer; forming a second mask pattern over the fifth insulating layer; forming dual damascene structure by performing an etching process; sequentially depositing a second conducting layer and a dielectric layer on the dual damascene structure; selectively removing some portion of the dielectric layer; depositing a third conducting layer over the dielectric layer; and planarizaing the top surface of the third conducting layer, the dielectric layer, and the second conducting layer by performing a CMP process.
|
