发明名称 |
Method and system for providing hierarchical self-checking in ASIC simulation |
摘要 |
A method and system for providing simulation of an integrated circuit during development of the integrated circuit is disclosed. The integrated circuit has an island that includes an interface. The method and system include a snooper, a checker and a generator. The snooper is coupled with an interface and is for obtaining an output provided by the island during simulation. The checker is coupled with an interface and is for checking the output to determine whether the output is a desired output. The generator is coupled with an interface and is for providing an input to the interface during simulation. The generator is coupled with a test case that directs the generator.
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申请公布号 |
US7072816(B1) |
申请公布日期 |
2006.07.04 |
申请号 |
US19990409940 |
申请日期 |
1999.09.30 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BULLIS BRYAN KEITH;SINGH RAJ KUMAR;WHITE FOSTER BEAVER |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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