| 摘要 |
In order to provide an interface circuit (100; 100') as well as a method for receiving and/or for decoding, in particular for recovering, data signals (D; R, G, B), in particular high speed data signals, for example high speed sequential digital data signals, wherein at least one sampling clock signal (SC), in particular at least one multi- phase sampling clock signal (PC[n-l:0]) with n different phases, and/or the data signals (D; R, G, B) are delayed, and wherein it is possible to optimize the components, in particular the analog components, for a fixed operating frequency, it is proposed that the sampling clock signal (SC), in particular the multi-phase sampling clock signal (PC[n-l:0]), is asynchronous - to at least one interface clock signal (IC), by which the interface circuit (100; 100'), in particular the input of the interface circuit (100; 100'), can be provided with, and/or to the data signals (D; R, G, B). |
