| 摘要 |
PROBLEM TO BE SOLVED: To reduce a circuit scale in a frequency divider circuit capable of generating a dividing clock at an arbitrary division ratio. SOLUTION: The frequency divider circuit comprises a counting circuit and a comparison circuit. The counting circuit counts a reference clock using a predetermined load value as a start value to output it to the comparison circuit, whereas the comparison circuit, when the counted value of the counting circuit becomes equal to a set value, outputs a load signal to the counting circuit so that counting is started with the load value again. By using a part of an output value of the counting circuit directly as the dividing clock, it is possible to reduce the number of comparison circuits to one where the two is required conventionally and an output flip-flop becomes unnecessary, so the circuit scale is reduced. COPYRIGHT: (C)2006,JPO&NCIPI
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