| 摘要 |
PROBLEM TO BE SOLVED: To provide a technique and structure applicable for making the layout design of an edge pad type chip by utilizing a layout of a center pad type chip. SOLUTION: A physical distance is shortened between an output pad 20 and a data outputting CMOS driver 10 so that an unwanted resistance is not applied between the output pad 20 and the data outputting CMOS driver 10, while a first control signal line 31 which is an ON/OFF controlling signal line of a pMOSFET 11 and a second control signal line 32 which is the ON/OFF controlling signal line of an nMOSFET 12 are elongated. In addition, the first control signal line 31 and the second control signal line 32 are juxtaposed adjacent to each other so that an inter-line capacity between the first control signal line 31 and the second control signal line 32 is reduced when data is output. COPYRIGHT: (C)2006,JPO&NCIPI
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