| 摘要 |
Semiconductor integrated circuit devices having SRAM cells and flash memory cells are provided. The devices include an integrated circuit substrate having an SRAM cell region, a flash memory cell region and a logic circuit region. An isolation layer is provided in a predetermined region of the substrate. The isolation layer defines a SRAM cell active region, a flash memory cell active region and a logic transistor active region in the SRAM cell region, the flash memory cell region and the logic circuit region, respectively. An SRAM cell gate pattern crosses over the SRAM cell active region. The SRAM cell gate pattern includes a main gate electrode and a dummy gate electrode which are sequentially stacked. A flash memory cell gate pattern crosses over the flash memory cell active region. The flash memory cell gate pattern includes a control gate electrode crossing over the flash memory cell active region as well as a floating gate interposed between the control gate electrode and the flash memory cell active region. A logic gate pattern crosses over the logic transistor active region. The logic gate pattern also includes a main gate electrode and a dummy gate electrode which are sequentially stacked. Related methods of fabricating semiconductor integrated circuit devices are also provided.
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