发明名称 Formation of junctions and silicides with reduced thermal budget
摘要 Method of formation of a metal-silicide layer ( 12, 13, 14, 18, 19 ) an a semiconductor substrate ( 1 ), the semiconductor substrate ( 1 ) including at least a dopant region ( 5 ); the dopant region ( 5 ) including an ultra-shallow junction region; the method including as a first step at least one impurity implantation process (IB dopant) for forming the dopant region ( 5 ); the method including as a second step at least one metal implantation process (IB metal) for forming the metal-silicide layer ( 12, 13, 18, 19 ) an the dopant region ( 5 ), and the method including, as a third step carried out after the first and the second step, a low-temperature annealing process wherein simultaneously the dopant region ( 5 ) is activated and the metal-silicide layer ( 12, 13, 14, 18, 19 ) is formed.
申请公布号 US2006141728(A1) 申请公布日期 2006.06.29
申请号 US20050559069 申请日期 2005.11.30
申请人 KONINKLIJKE PHILIPS ELECTRONICS N.V. 发明人 PAWLAK BARTLOMIEJ J.
分类号 H01L21/336;H01L21/265;H01L21/28;H01L21/285 主分类号 H01L21/336
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