发明名称 PROGRAMMABLE DIGITAL DELAY
摘要 A method of delaying successive first and second input signals by first and second different selectable time periods using a programmable delay line comprising a sequence of delay elements, each introducing a delay, the method comprising the steps of: providing a control signal to each delay element, the control signal selectively being in a first logic state or a second logic state wherein in a first logic state the delay element selects an input from an adjacent delay element thereby to select the delay elements as part of a set of delay elements introducing said selectable time period and in a second logic state the delay element is not selected in the set; setting the control signals for a first number of adjacent delay elements to the first logic state to introduce the first selectable time period wherein the control signals for the delay elements in the sequence not in the first number are set to the second logic state; and setting the control signals of a second number of adjacent delay elements to the first logic state to introduce a second selectable time period, wherein the control signals for the delay elements in the sequence not in the second number are set to the second logic state; whereby the reconfiguration time between the first and second input signals is less than the maximum delay introduced by the sequence of delay elements.
申请公布号 WO2006067393(A2) 申请公布日期 2006.06.29
申请号 WO2005GB04877 申请日期 2005.12.16
申请人 STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED;WARREN, ROBERT, GEOFFREY 发明人 WARREN, ROBERT, GEOFFREY
分类号 H03K5/13;H03K5/00 主分类号 H03K5/13
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