发明名称 |
DIGITAL TO ANALOGUE CONVERSION |
摘要 |
A method of Digital to Analogue conversion of an input signal D° for suppressing the effect of clock-jitter in a Delta-Sigma analogue to digital converter, or class D amplifier, comprises charging a capacitor (414) to a reference voltage value (V ref) during a first phase of a clock signal, discharging the capacitor during a second phase of the clock signal, wherein the discharge is regulated by a biased transistor (418. 419), responsive to the voltage on the capacitor, in a first part of the second phase to provide an approximately constant discharge current, and regulated in a second part of the second phase for rapidly discharging the capacitance means before the end of the second phase; and providing an output (Ud OUT) as a function of the discharge current and the input signal D°, The output signal Ud may be applied as a feedback signal to a loop filter in a Delta-Sigma converter Alternatively the output may represent the output of a Class D amplifier. |
申请公布号 |
WO2006067382(A1) |
申请公布日期 |
2006.06.29 |
申请号 |
WO2005GB04832 |
申请日期 |
2005.12.14 |
申请人 |
UNIVERSITY OF WESTMINSTER;KALE, IZZET;MORLING, RICHARD, CHARLES, SPICER;ZARE-HOSEINI, HASHEM |
发明人 |
KALE, IZZET;MORLING, RICHARD, CHARLES, SPICER;ZARE-HOSEINI, HASHEM |
分类号 |
H03M3/00;H03M1/08;H03M1/74 |
主分类号 |
H03M3/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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