发明名称 FIFO MEMORY
摘要 PROBLEM TO BE SOLVED: To provide an FIFO memory of which power consumption is reduced by improving a reliability. SOLUTION: The changing amount of write data to be transmitted to a dual port memory 108 is reduced by such a manner that: a buffer circuit 105 temporarily holds previously written write data; a comparator circuit 106 compares write data newly to be written with the previously written write data for every bit and outputs 1 when more than half of bit widths are being changed; and an encoder circuit 107 outputs whole bits of the write data by inverting them when 1 is represented in the comparison result of the comparator circuit 106, and it outputs the write data as they are when 0 is represented in the result of the comparator circuit 106. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006172672(A) 申请公布日期 2006.06.29
申请号 JP20040367519 申请日期 2004.12.20
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 YASUNAGA KOTA
分类号 G11C7/00 主分类号 G11C7/00
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