发明名称 FAULT-TOLERANT COMPUTER RESETTING METHOD AND ITS SYSTEM
摘要 <p><P>PROBLEM TO BE SOLVED: To make it possible to completely synchronize a fault-tolerant computer between modules to reset it. <P>SOLUTION: A method for resetting a fault-tolerant computer is provided with; a step which generates a resetting request signal with one of the modules; a step which branches the resetting request signal into a first resetting request signal and a second resetting signal; a step which transmits the second resetting request signal to another module; a step which delays the first resetting request signal in one of the modules by time required to transmit the second resetting request signal to another module; a step which resets a CPU included in one of the modules with a first CPU resetting signal generated based on the first resetting request signal delayed in one of the modules; and a step which resets a CPU included in another module with a second CPU resetting signal generated based on the second resetting request signal transmitted to another module. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p>
申请公布号 JP2006172391(A) 申请公布日期 2006.06.29
申请号 JP20040367749 申请日期 2004.12.20
申请人 NEC CORP 发明人 ABE SHINJI
分类号 G06F1/24 主分类号 G06F1/24
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