发明名称 |
Method for analyzing circuit pattern defects and a system thereof |
摘要 |
A system for analyzing defects in electronic circuit patterns, including: comparing position information of structural defects with position information of electrical faults and extracting corroborated defects having common position information between the structural defects and electrical faults; classifying images of extracted corroborated defects into critical defect images and non-critical defect images based on a pre-stored classification rule which defines critical and non-critical defects by referring to images of defects, position information of defects, and results of performing an electronic test; modifying the pre-stored classification rule by correcting classification of classified defect images displayed on the screen; and repeating the operations for each subsequent object, wherein for each present object under inspection, using a modified pre-stored classification rule with respect to a previous object, as the pre-stored classification rule for the operations with respect to the present object.
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申请公布号 |
US2006140472(A1) |
申请公布日期 |
2006.06.29 |
申请号 |
US20060356210 |
申请日期 |
2006.02.17 |
申请人 |
SHIMODA ATSUSHI;ISHIMARU ICHIROU;TAKAGI YUJI;TAMURA TAKUO;HAMAMURA YUICHI;WATANABE KENJI;OZAWA YASUHIKO;ISOGAI SEIJI |
发明人 |
SHIMODA ATSUSHI;ISHIMARU ICHIROU;TAKAGI YUJI;TAMURA TAKUO;HAMAMURA YUICHI;WATANABE KENJI;OZAWA YASUHIKO;ISOGAI SEIJI |
分类号 |
G01N21/88;G06K9/00;G01N21/94;G06T7/00;H01L21/66 |
主分类号 |
G01N21/88 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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