发明名称 |
Operation methods for a non-volatile memory cell in an array |
摘要 |
A method of reducing gate disturb in a charge-trapping layer memory cell by applying different Vpass voltages to different sides of a selected wordline. A higher Vpass voltage is used to pass higher source/drain voltage and a lower Vpass voltage is used to pass a lower source/drain voltage. By controlling the Vpass voltages on different sides of a selected wordline, it is possible to reduce a vertical field that is established in a gate region when the Vpass voltages are applied. A reduced vertical field results in suppressed gate disturb. The method also includes a novel bit-line biasing scheme that may further reduce the vertical field and thereby may further suppress gate disturb, particularly in an array of memory cells.
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申请公布号 |
US2006140000(A1) |
申请公布日期 |
2006.06.29 |
申请号 |
US20040020269 |
申请日期 |
2004.12.27 |
申请人 |
LIAO YI Y;YEH CHIH C;TSAI WEN J |
发明人 |
LIAO YI Y.;YEH CHIH C.;TSAI WEN J. |
分类号 |
G11C16/04;G11C16/06 |
主分类号 |
G11C16/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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