| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock synchronization scheme and a data transmission system for reducing the influence of jitters due to variation in a packet receiving timing in a receiver side, if a system clock of a transmitter side must be synchronized with that of the receiver side when stream data are distributed in a network having a varying passing time and a packet including time stamp information is transmitted from the transmitter side. <P>SOLUTION: A receiver 13 takes an RTP time stamp value out of an RTP packet and gives it to a time stamp comparing circuit 132, and the circuit 132 inputs a result of comparison of the given time stamp value with a time stamp value of a time stamp circuit 133 into a micro controller 135. The micro controller 135 performs arithmetic operation including smoothing of a comparison result, and a PLL 137 is controlled on the basis of that, thereby reducing the influence of the jitters due to variation in the packet receiving timing. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
