发明名称 |
METHOD FOR PROVIDING LAYOUT DESIGN AND PHOTO MASK |
摘要 |
A method for providing the layout design of semiconductor integrated circuit that is capable of promoting the reduction of the circuit pattern area is provided. A hole pattern is disposed at the mesh point which is an intersecting point of mutually orthogonal virtual grid lines and another hole pattern is not disposed at the adjacent mesh point that is the closed mesh point having the hole pattern thereon. |
申请公布号 |
KR100593219(B1) |
申请公布日期 |
2006.06.28 |
申请号 |
KR20040110039 |
申请日期 |
2004.12.22 |
申请人 |
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发明人 |
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分类号 |
G03F1/36;G03F1/70;G06F17/50;H01L21/027;H01L21/82;H01L27/02;H01L27/118 |
主分类号 |
G03F1/36 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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