发明名称 Self test of a semiconductor circuit
摘要 <p>A semiconductor device includes an output path; an output test signal an input path; and a test signal generating circuit. The output test signal is delayed to produce a delayed output test data signal. The output test signal is delayed to produce a delayed output test data signal. The test signal generating circuit generates an input test data signal from said output test data signal and said delayed output test data signal to change at least one of an amplitude and a phase of an output test data signal which is generated from a test data in the semiconductor device and transferred on the output path, and supplies the input test data signal onto the input path. The output path and the input path are tested by using the output test data signal and the input test data signal, respectively.</p>
申请公布号 EP1674876(A1) 申请公布日期 2006.06.28
申请号 EP20050028224 申请日期 2005.12.22
申请人 NEC ELECTRONICS CORPORATION 发明人 MATSUMOTO, KATSUHIDE;SOUDA, MASAAKI;MITSUISHI, MASAFUMI;SAKAI, SHINGO;KATOU, HIROMU
分类号 G01R31/317;G01R31/3187 主分类号 G01R31/317
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