发明名称 |
Structure and method to reduce drain induced barrier lowering |
摘要 |
Embodiments of the present invention include a method for manufacturing a transistor comprising forming a gate conductor above a semiconductor substrate; forming a lightly doped implant region within the substrate, wherein the lightly doped implant region is substantially on the source side of the transistor; and forming a counter doping implant region within the substrate, wherein the counter-doping implant region is substantially on the drain side and wherein the counter-doping reduces the net channel impurity concentration on the drain side.
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申请公布号 |
US7067381(B1) |
申请公布日期 |
2006.06.27 |
申请号 |
US20030636336 |
申请日期 |
2003.08.06 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
THURGATE TIMOTHY;WONG NGA-CHING |
分类号 |
H01L21/331 |
主分类号 |
H01L21/331 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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