Semiconductor memory device having row path control circuit and operating method thereof

摘要

A semiconductor memory device having a row path control circuit for reducing a peak current. The semiconductor memory device including: a bank controller for activating the bank signal as a first and a second bank driving signals; an inner address counter for generating an internal address in response to the refresh signal; a row address latch for selecting one of the internal address and the inputted address; a first decoder for decoding the row address in response to the first bank driving signal; a second decoder for decoding the row address in response to the second bank driving signal; a first row controller for activating a first amplifier enable signal in response to the first bank driving signal; a second row controller for activating a second amplifier enable signal in response to the second bank driving signal; and a amplifier for amplifying memory cell data of the activated word line.