发明名称 Metal-insulator-metal capacitor fabricating method for integrated circuit, involves etching insulating layer to form spacer surrounding upper electrode, and forming lower electrode and dielectric medium
摘要 <p>#CMT# #/CMT# The method involves depositing a metallic layer, an insulating layer and another metallic layer successively. An upper electrode (4) is formed on one metallic layer. Another insulating layer is etched to form a spacer (14) surrounding the electrode. A lower electrode (2) and a dielectric medium (3) are formed by retracting metallic and insulating layers not covered by the upper electrode or the spacer. Interconnection lines are formed. #CMT# : #/CMT# An independent claim is also included for an integrated circuit including a capacitor. #CMT#USE : #/CMT# Used for fabricating a metal-insulator-metal capacitor in an interconnection layer of an integrated circuit (claimed), and for fabricating planar capacitor and three-dimensional capacitor. #CMT#ADVANTAGE : #/CMT# The spacer protects edge of the upper electrode during later stages of fabrication of the capacitor, so that the edge is not covered with parasitic conducting deposits and is not damaged during etching stages. The method avoids a need for photolithography mask, and makes the width of retraction of the upper electrode with respect the lower electrode constant along their periphery using the spacer. The spacer allows realizing an auto-alignment between the two electrodes to prevent dispersion due to alignment between two successive masks, so that average retraction dimension can be reduced and markings required for alignment errors are suppressed. The method therefore reduces surface occupied the capacitor on the interconnection layer. The spacer also prevents short-circuit between the electrodes, allows creating interconnection lines at the level of the capacitor and reduces the cost and risk of short-circuits, premature breakdowns and current leakages. #CMT#DESCRIPTION OF DRAWINGS : #/CMT# The drawing shows a capacitor. 2 : Lower electrode 3 : Dielectric medium 4 : Upper electrode 5 : Inter-connection lines 14 : Spacer #CMT#INORGANIC CHEMISTRY : #/CMT# The metallic layers are made of titanium nitrate, tantalum nitrate and tungsten. The insulating layers are made of aluminum oxide, tantalum oxide and hafnium oxide.</p>
申请公布号 FR2879815(A1) 申请公布日期 2006.06.23
申请号 FR20040013415 申请日期 2004.12.16
申请人 STMICROELECTRONICS SA SOCIETE ANONYME 发明人 GIRAUDIN JEAN CHRISTOPHE;CREMER SEBASTIEN;DELPECH PHILIPPE
分类号 H01L27/06;H01L21/02 主分类号 H01L27/06
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