| 摘要 |
PROBLEM TO BE SOLVED: To provide a buffer circuit and its control method which perform buffering of data between a synchronous circuit and an asynchronous circuit: and to provide an interface circuit and its control method which performs data transfer control between the synchronous memory circuit and asynchronous circuit being used for the buffer circuit and its control method. SOLUTION: The data buffer circuit 10 sandwiched between an image processing system 1A and a main system 2 comprises a RAM 130 with one port, a control signal generation section 110, an address generation section 100, and a first selector 113. In access to the RAM 130 with one port, the first selector 113 selectively outputs a current cycle address IA (14:0) to an address AD (14:0) of the RAM 130 with one port at the time of write access, and selectively outputs a next cycle address IA1(14:0) to the address AD (14:0) of the RAM 130 with one port at the time of read access. COPYRIGHT: (C)2006,JPO&NCIPI
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