发明名称 Circuit re-synthesis and method for delay variation tolerance
摘要 By adding redundant logic gates into a circuit without changing function of the whole circuit, the present invention can tolerate certain delay variations. The present invention can be applied in the IC industries to improve the yield in semiconductor manufacturing.
申请公布号 US2006132169(A1) 申请公布日期 2006.06.22
申请号 US20040014170 申请日期 2004.12.17
申请人 NATIONAL TSING HUA UNIVERSITY 发明人 CHANG SHIH-CHIEH
分类号 H03K19/003 主分类号 H03K19/003
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