| 摘要 |
PROBLEM TO BE SOLVED: To provide a refresh control circuit for a DRAM in which REF timing is controlled so that a peak current when the DRAM is refreshed is controlled effectively when a plurality of the DRAMs exist. SOLUTION: A first DRAM control circuit (10a) has a first refresh control means (16a) for performing refresh of a first DRAM(11a), and a first refresh request signal transmitting means (16a) outputting a first refresh request signal(20) to a second DRAM control circuit(10b) corresponding to refresh timing of the first DRAM, the second DRAM control circuit(10b) is a refresh control circuit of DRAM having a second refresh control means(16b) for performing refresh of the second DRAM(11b), based on the first refresh request signal transmitted by the first refresh request signal transmitting means. COPYRIGHT: (C)2006,JPO&NCIPI
|
