发明名称 |
Multi-thickness dielectric for semiconductor memory |
摘要 |
A process provides a gate dielectric layer of a first thickness for a memory array and for certain peripheral circuits on the same substrate as the memory array. High-voltage peripheral circuits are provided with a gate dielectric layer of a second thickness. Low-voltage peripheral circuits are provided with a gate dielectric layer of a third thickness. The process provides protection from subsequent process steps for a gate dielectric layer. Shallow trench isolation allows the memory array cells to be extremely small, thus providing high storage density.
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申请公布号 |
US2006134864(A1) |
申请公布日期 |
2006.06.22 |
申请号 |
US20040020402 |
申请日期 |
2004.12.22 |
申请人 |
HIGASHITANI MASAAKI;PHAM TUAN |
发明人 |
HIGASHITANI MASAAKI;PHAM TUAN |
分类号 |
H01L21/336 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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