| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a PLL circuit for reducing an amount of a phase offset caused by a charge pump circuit. <P>SOLUTION: The PLL circuit includes: a phase frequency comparator (PFD) 10 for comparing a phase of an input signal Vin with a phase of an output signal Vout; the charge pump circuit 20 for charging a capacitor 21 in an activate state of an UP signal UP from the PFD and discharging the capacitor 21 in an active state of a DOWN signal DN to output a terminal voltage of the capacitor 21 as a control voltage Vcont; and a VCO 30 for outputting an output signal with a frequency in accordance with the Vcont, wherein an output of the VCO is fed back to the PFD as an output signal, the PDF includes: a delay amount adjustment circuit 14 that controls the PFD to reset the UP and the DN by a delay of a prescribed delay amount respectively when the UP and the DN are activated; and a comparison amplifier 40 for comparing a reference voltage Vref corresponding to a control voltage when both the UP and the DN are activated with the Vcont and outputting control signals Vup, Vdn to the delay amount adjustment circuit 14, and the PDF adjusts the pulse width of the UP and the DN in accordance with a current offset characteristic of the charge pump circuit 20. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
