发明名称 |
LOW-VOLTAGE, MULTIPLE THIN-GATE OXIDE AND LOW-RESISTANCE GATE ELECTRODE |
摘要 |
A method of making a memory array and peripheral circuits together on a single substrate forms a dielectric layer, floating gate layer, inter-layer dielectric and mask layer across all regions of the substrate. Subsequently these layers are removed from the peripheral regions and dielectrics of different thicknesses are formed in the peripheral regions according to the voltages of the circuits in these regions. A conductive layer is formed over the memory array and the peripheral circuits to form control gates in the memory array and form gate electrodes in the peripheral regions.
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申请公布号 |
US2006134845(A1) |
申请公布日期 |
2006.06.22 |
申请号 |
US20040021693 |
申请日期 |
2004.12.22 |
申请人 |
PHAM TUAN;HIGASHITANI MASAAKI |
发明人 |
PHAM TUAN;HIGASHITANI MASAAKI |
分类号 |
H01L21/8238 |
主分类号 |
H01L21/8238 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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