| 摘要 |
PROBLEM TO BE SOLVED: To accomplish an interface circuit capable of reducing a layout area. SOLUTION: A source of an NMOS transistor N1 is connected to an external input terminal VIN of -1V to 6V, a source of a PMOS transistor P1 is connected to its source, and an inverter is connected to its drain. When threshold voltages VTN1, VTP1 of N1 and P1 are set to 1V and gate voltages VGN1, VGP1 are set to 4V and 0V, respectively, the voltage to be given to a node A is limited within a range of -1V to 3V. Furthermore, the voltage to be given to a node B is limited within a range of 1V to 3V. Namely, the range of output voltages of N1 and P1 can be suppressed narrower than the range of voltages to be given to the external input terminal VIN. COPYRIGHT: (C)2006,JPO&NCIPI
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