| 摘要 |
PROBLEM TO BE SOLVED: To provide an A/D converter the linearity of which is enhanced. SOLUTION: The A/D converter 100 is provided with a monitor unit 50 in addition to: a reference voltage circuit 30 for generating a reference voltage; a first conversion unit 10 for generating data of high-order bits; a second conversion unit 20 for generating data of low-order bits; and a composite circuit 40. The monitor unit 50 monitors the data Sf of the low-order bits produced by the second conversion unit 20. The monitor unit 50 predicts offsets of comparators CMPc1 to CMPc3 of a first comparison unit 12 from the data of the low-order bits. When the monitor unit 50 monitors the data and the monitoring results in that data Sf' of the low-order bits are included in an upper side overlap range, a first reference voltage generating section 32 shifts a dense reference voltage Vrc toward a lower voltage, and when the monitoring results in that the data Sf' of the low-order bits are included in a lower side overlap range, the first reference voltage generating section 32 shifts a dense reference voltage Vrc toward a higher voltage. COPYRIGHT: (C)2006,JPO&NCIPI
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