CMOS NVM BITCELL AND INTEGRATED CIRCUIT

摘要

A non-volatile memory bitcell structure (10) is disclosed that includes a dual capacitor structure. A first metal-insulator-metal (MIM) capacitor (14) having a first capacitance value includes a first top plate (20), a first bottom plate (16), and a first dielectric (18) disposed in-between the first top plate and the first bottom plate. A second metal-insulator-metal (MIM) capacitor (22) having a second capacitance value includes a second top plate (26), a second bottom plate (16), and a second dielectric (24) disposed in-between the second top plate and the second bottom plate. An element (16) of the first MIM capacitor (14) is electrically coupled in common with an element (16) of the second MIM capacitor (22). In addition, the first capacitance value is greater than the second capacitance value.