| 摘要 |
PROBLEM TO BE SOLVED: To provide a system for sampling an analog or digital data signal at a relatively high rate utilizing relatively slow circuitry. SOLUTION: A system 40 includes several sample and hold circuits 42 to 50, each of which receives the data signal. The sample and hold circuits are clocked by respective clock signalsΦ<SB>1</SB>...Φ<SB>n</SB>that are at the same frequency but equally phased apart from each other. Each of the sample and hold circuits is connected to a series of shift registers 62 to 70. The shift registers operate to sequentially store samples S<SB>1</SB>to S<SB>n</SB>obtained by their respective sample and hold circuits. Outputs 82 to 90 of the shift registers may be applied to the column drivers of a conventional matrix display. COPYRIGHT: (C)2006,JPO&NCIPI
|
