发明名称 METHOD OF VERIFYING LOGICAL CIRCUIT SYSTEM
摘要 <P>PROBLEM TO BE SOLVED: To automatically manage/control fundamental process control and sequence control in test execution during system verification of a logical circuit. <P>SOLUTION: A program has a means for randomly executing a test execution process and a means for managing the control and termination of the process, and has a mechanism for automatically conducting these means, in the system verification of the logical circuit. <P>COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006163981(A) 申请公布日期 2006.06.22
申请号 JP20040356304 申请日期 2004.12.09
申请人 CANON INC 发明人 SONO SHIZUKA
分类号 G06F11/22 主分类号 G06F11/22
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