| 摘要 |
PROBLEM TO BE SOLVED: To provide an analysis structure for failure analysis in a semiconductor device, and to provide a failure analysis method that uses the same. SOLUTION: The device comprises a plurality of analytic fields, disposed on a predetermined region of a semiconductor substrate, semiconductor transistors arranged in the analytic fields to form an array structure, and wordline and bitline structures, arranged on the analytic fields, connecting the semiconductor transistors with each other in a horizontal direction and a vertical direction. In this case, the bitline structures are configured as different structures in each of the plurality of analytic fields. Thereby, the development period of the semiconductor device can be minimized, and market monopoly of the semiconductor device becomes possible. COPYRIGHT: (C)2006,JPO&NCIPI
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