| 摘要 |
The present invention relates to a method of whole-chip electrostatic discharge protection, wherein the chip has a first metallic layer and a second metallic layer, and each surrounds the chip along the trail keeping an appropriate spacing away from the perimeter of the chip separately, and in contrast to the first type semiconductor substrate, a second type semiconductor well is formed below the first metallic layer. The second type semiconductor well, which surrounds the chip along the trail keeping an appropriate spacing away from the perimeter of the chip, can function as a large capacitor to store the discharged electricity. Thereby, the electrostatic discharge protection of the whole chip can be promoted with no increasing chip area needed and without changing the original design and manufacture process of IC.
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