| 摘要 |
An integrated circuit capacitor having a bottom plate 50 a, a dielectric layer 250 ', and a ferromagnetic top plate 20 a. Also, a method of manufacturing an integrated circuit on a semiconductor wafer. The method comprising forming a bottom plate of a capacitor 50 a and a bottom portion of an induction coil 50 a, forming an etch stop layer 250 ', forming a ferromagnetic capacitor top plate 20 a and a ferromagnetic core 20 b, forming a top portion of the induction coil 50 b plus vias 50 c that couple the top portion of the induction coil 50 b to the bottom portion of the induction coil 50 c.
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