PARALLEL DECISION FEEDBACK EQUALIZER FOR STABLE EQUALIZATION OF HIGH SPEED DATA

摘要

A parallel decision feedback equalizer for stable equalization of high speed data is provided. The parallel decision feedback equalizer includes: a first parallel threshold decision element having at least two parallel threshold decision elements each having a different threshold value; a first multiplexer for multiplexing data from the first parallel threshold decision element based on a second output from a second multiplexer; a first D flip-flop for delaying a first output from the first multiplexer by a unit data clock pulse; a second parallel threshold decision element having a third delay unit and at least two parallel threshold decision elements each having a different threshold value; the second multiplexer for multiplexing data from the second parallel threshold decision element based on a delayed output from the first D flip-flop; and a second D flip-flop for delaying the second output from the second multiplexer by the unit data clock pulse.