| 摘要 |
<p>A single-event upset tolerant random access memory cell (20) is disclosed that includes first and second sets of access transistors (31, 32, 33, 34) along with a first and second sets of dual-path inverters. The first set of access transistors (31, 32) is coupled to a first bitline BL, and the second set of access transistors (33, 34) is coupled to a second bitline BL that is complementary to the first bitline (BL). The first set of dual-path inverters (21, 22, 23, 24) is coupled to the first set of access transistors (31, 32); and the second set of dual-path inverters (25, 26, 27, 28) is coupled to the second set of access transistors (33, 34).</p> |
