| 摘要 |
A fault-tolerant computer has a pair of duplex systems having respective CPU subsystems that are operable identically in lock-step synchronism. Each of the duplex systems has a CPU, a main storage unit, a CP U bus controller, and a DMA controller. The CPU and the main storage unit are included in each of the CPU subsystems. The CPU bus controller continuously operates the CPU of its own system even if it detects an asynchronous operation while the CPU subsystems are operating in synchronism with each other. Even if the asynchronous operation is detected, the DMA controller holds a DMA transfer process for transferring data stored in the main storage unit o f its own system or the other system to the main storage unit of the other system or its own system after the asynchronous operation is detected until a certain time is reached.
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