| 摘要 |
To multiplex more than four channels of data signals by generating frequency-divided clock signals using toggle flip-flop circuits (TFF), while avoiding any possible phase shift relationship between the frequency-divided clock signals attributed to an indefinite initial state of the TFF, there is provided a clock generator circuit comprising a plurality of toggle flip-flop circuits (TFF1, TFF2) connected in series, capable of outputting a pair of frequency-divided clock signals with different phases; and a delay circuit(DFF1), connected to the toggle flip-flop circuit(TFF2), capable of outputting a clock signal with a phase shifted with respect to the phases of the pair of frequency-divided clock signal phases by delaying either one or both of the pair of frequency-divided clock signals being outputted from the toggle flip-flop circuit (TFF2).
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