| 发明名称 |
Copper recess process with application to selective capping and electroless plating |
| 摘要 |
An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features. |
| 申请公布号 |
US7064064(B2) |
申请公布日期 |
2006.06.20 |
| 申请号 |
US20050058783 |
申请日期 |
2005.02.16 |
| 申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CHEN SHYNG-TSONG;DALTON TIMOTHY J.;DAVIS KENNETH M.;HU CHAO-KUN;JAMIN FEN F.;KALDOR STEFFEN K.;KRISHNAN MAHADEVAIYER;KUMAR KAUSHIK;LOFARO MICHAEL F.;MALHOTRA SANDRA G.;NARAYAN CHANDRASEKHAR;RATH DAVID L.;RUBINO JUDITH M.;SAENGER KATHERINE L.;SIMON ANDREW H.;SMITH SEAN P. E.;TSENG WEI-TSU |
| 分类号 |
H01L21/44;H01L21/768;H01L23/532 |
主分类号 |
H01L21/44 |
| 代理机构 |
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