| 摘要 |
An apparatus for speculatively forwarding storehit data in a microprocessor pipeline. First and second virtual address comparators compare a virtual load address with first and second virtual store addresses to generate a virtual match signal for indicating whether first and second storehit data is likely present in a store buffer and a result forwarding cache, respectively. If the first and second storehit data are both present the second storehit data is newer than the first storehit data. First and second physical address comparators compare a physical load address translated from the virtual load address with first and second physical store addresses translated from the plurality of virtual store addresses to generate a physical match signal for indicating whether the first and second storehit data is certainly present in the store buffer and the result forwarding cache, respectively. Forwarding logic forwards the second storehit data present in the store buffer in response to the virtual match signal indicating no match between the virtual load address and the second virtual store addresses but a match between the virtual load address and the first virtual store address, prior to generation of the physical match signal. Control logic receives the virtual and physical match signals and generates a stall signal for stalling the pipeline subsequent to the forwarding logic forwarding the storehit data From the store buffer if the physical match signal indicates a match between the physical load address and the second physical store addresses although the virtual match signal previously indicated no match between the virtual load address and the second virtual store addresses, until correct data specified by the physical load address is provided to replace the previously forwarded second storehit data.
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