| 摘要 |
A memory circuit requiring refresh operations, the memory circuit includes a memory core having memory cells, and a memory control circuit which, for M external operation cycles, where M is greater than or equal to 2, has N internal operation cycles, where N is greater than M and less than 2M. The memory circuit also includes a refresh command generation circuit which generates refresh commands, and wherein the N internal operation cycles includes first internal operation cycles which execute external commands corresponding to the external operation cycles, and second internal operation cycles which execute the refresh commands, and the refresh command generation circuit generates the refresh commands according to a reception of the external command.
|
