发明名称 Metal gate engineering for surface p-channel devices
摘要 A semiconductor device, such as a CMOS device, having gates with a high work function in PMOS regions and low work functions in NMOS regions and a method of producing the same. Using nitrogen implantation or plasma annealing, a low work function W (or CoSi<SUB>x</SUB>)/TaSi<SUB>x</SUB>N<SUB>y</SUB>/GOx/Si gate stack is formed in the NMOS regions while a high work function W (or CoSi<SUB>x</SUB>)/Ta<SUB>5</SUB>Si<SUB>3</SUB>/GOx/Si gate stack is formed in the PMOS regions. The improved process also eliminates the need for a nitrided GOx which is known to degrade g<SUB>m </SUB>(transconductance) performance. The materials of the semiconductor devices exhibit improved adhesion characteristics to adjacent materials and low internal stress.
申请公布号 US7064390(B2) 申请公布日期 2006.06.20
申请号 US20040012049 申请日期 2004.12.14
申请人 发明人
分类号 H01L27/12 主分类号 H01L27/12
代理机构 代理人
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