发明名称 System and method for reducing design cycle time for designing input/output cells
摘要 A method and system is disclosed for generating a desired input/output (I/O) cell based on a basic cell from a library. After identifying a configuration requirement for a desired I/O cell to be used for an integrated circuit design, at least one basic cell is selected, the basic cell having a base component for generating the desired I/O cell to meet the configuration requirement. A connection template is generated having one or more programmable connection points identified thereon, the programmable connection points identifying locations for making connections to one or more feature components of the basic cell. The selected basic cell and the connection template are combined to generate a design file, wherein the design file corresponds to the desired I/O cell with the predetermined feature components of the basic cell integrated with the basic component to satisfy the configuration requirement. The disclosed method reduces the design cycle-time as well as circuit-library maintenance and update effort.
申请公布号 US7062740(B2) 申请公布日期 2006.06.13
申请号 US20030444907 申请日期 2003.05.22
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. 发明人 CHEN KER-MIN;SONG MING-HSIANG;HU CHANG-FEN
分类号 G06F17/50;H03K19/00 主分类号 G06F17/50
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