发明名称 |
Method and system for obtaining a feasible integer solution from a half-integer solution in hierarchical circuit layout optimization |
摘要 |
A method ( 300 ) and system ( 500 ) for optimizing a circuit layout based on layout constraints ( 308 ) and objectives ( 312 ). The method includes solving a linear program so as to obtain a rational solution whose variables are either whole or half integer. The tight constraints and objectives involving variables whose solution are a half integer are reduced to a 2-SAT problem, which is analyzed to determine its satisfiability. If the 2-SAT problem is not satisfiable, one or more objectives are removed so as to make the 2-SAT problem satisfiable. Any half-integer results of the linear program are rounded according to the truth assignment that satisfies the 2-SAT problem. The rounded results are used to create the circuit layout.
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申请公布号 |
US7062729(B2) |
申请公布日期 |
2006.06.13 |
申请号 |
US20040946677 |
申请日期 |
2004.09.22 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
GRAY MICHAEL S.;HIBBELER JASON D.;TELLEZ GUSTAVO E.;WALKER ROBERT F. |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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